NXP Semiconductors MPC5606S - Chapter 9; Emios Clocking Configuration

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
234 Freescale Semiconductor
9.1.3 eMIOS clocking configuration
The clocking configurations of the eMIOS200_0 and eMIOS200_1 modules on this device are shown in
Figure 9-1.
Figure 9-1. eMIOS clocking configuration
9.1.4 MPC5606S family comparison
The following table shows the required split of eMIOS channel functionality across the MPC5606S family
as a function of flash memory size.
9.1.5 Channel Types
The channels of the eMIOS200_0 and eMIOS200_1 blocks on this device are implemented using a variety
of different channel configurations. The available modes of operation for each channel are shown in
Table 9-2 and Table 9-3.
Table 9-1. eMIOS total channel summary
256 KB 512 KB 1 MB
16-bit OPWM 16 16 16
16-bit IC/OC 8 8 8
FMPLL_0
eMIOS200_0
CGM_AC1_SC[SELCTL]
Modulated clock
FMPLL_1
eMIOS200_1
Non-modulated clock
8 Channel IC/OC
8 Channel OPWM
8 Channel OPWM
16 MHz IRC
4-16 MHz FXOSC
(in MC_CGM)
CGM_AC2_SC[SELCTL]
(in MC_CGM)