Periodic Interrupt Timer (PIT)
MPC5606S Microcontroller Reference Manual, Rev. 7
974 Freescale Semiconductor
• Independent timeout periods for each timer
27.2 Signal description
The PIT module has no external pins.
27.3 Memory map and register description
This section provides a detailed description of all registers accessible in the PIT module.
27.3.1 Memory map
Table 27-1 gives an overview on all PIT registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
NOTE
Reserved registers will read as 0, writes will have no effect.
Table 27-1. PIT memory map
Address offset Use Access
0x000 PIT Module Control Register R/W
0x004–0x0FC Reserved R
0x100–0x10C Timer Channel 0
1
1
See Ta bl e 27-2
0x110–0x11C Timer Channel 1
1
0x120–0x12C Timer Channel 2
1
0x130–0x13C Timer Channel 3
1
0x140–0x1FC Reserved R
Table 27-2. Timer Channel n
Address offset Use Access
Channel + 0x00 Timer Load Value Register R/W
Channel + 0x04 Current Timer Value Register R
Channel + 0x08 Timer Control Register R/W
Channel + 0x0C Timer Flag Register R/W
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