NXP Semiconductors MPC5606S - User Multiple Input Signature Register 1 (UMISR1)

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
620 Freescale Semiconductor
17.3.6.15 User Multiple Input Signature Register 1 (UMISR1)
The Multiple Input Signature Register provides a mean to evaluate the Array Integrity.
The User Multiple Input Signature Register 1 represents the bits 63-32 of the whole 144 bits word (2
Double Words including ECC).
The UMISR1 Register is not accessible whenever MCR.DONE or UT0.AID are low: reading returns
indeterminate data while writing has no effect.
17.3.6.16 User Multiple Input Signature Register 2 (UMISR2)
Address Offset: 0x0004C Reset value: 0x00000000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS06
3
MS06
2
MS06
1
MS06
0
MS05
9
MS05
8
MS05
7
MS05
6
MS05
5
MS05
4
MS05
3
MS05
2
MS05
1
MS05
0
MS04
9
MS04
8
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MS04
7
MS04
6
MS04
5
MS04
4
MS04
3
MS04
2
MS04
1
MS04
0
MS03
9
MS03
8
MS03
7
MS03
6
MS03
5
MS03
4
MS03
3
MS03
2
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-38. User Multiple Input Signature Register 1 (UMISR1)
Table 17-55. UMISR1 field descriptions
Field Description
0:31 MS063-032: Multiple input Signature 063-032 (Read/Write)
These bits represent the MISR value obtained accumulating the bits 63-32 of all the pages read from the
flash memory.

The MS can be seeded to any value by writing the UMISR1 register.
Address Offset: 0x00050 Reset value: 0x00000000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MS09
5
MS09
4
MS09
3
MS09
2
MS09
1
MS09
0
MS08
9
MS08
8
MS08
7
MS08
6
MS08
5
MS08
4
MS08
3
MS08
2
MS08
1
MS08
0
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MS07
9
MS07
8
MS07
7
MS07
6
MS07
5
MS07
4
MS07
3
MS07
2
MS07
1
MS07
0
MS06
9
MS06
8
MS06
7
MS06
6
MS06
5
MS06
4
rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-39. User Multiple Input Signature Register 2 (UMISR2)