Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1054 Freescale Semiconductor
30.5.4 Power saving features
The QuadSPI supports three power-saving strategies:
• Stop mode
• Module Disable mode—Clock gating of non-memory mapped logic
• Clock gating of slave bus signals and clock to memory-mapped logic
Like all power saving features, the Stop mode requires logic external to the QuadSPI module for power
management and clock gating control. Stop mode
The QuadSPI supports the global signal Stop mode protocol using the ipg_stop ipg_stop_ack
handshake. By default the ipg_stop_ack signal is de-asserted. When a request is made to enter Stop mode,
the QuadSPI block acknowledges the request by asserting ipg_stop_ack when it is ready to have its clocks
shut off. Depending from the mode of operation the following conditions must be met for the assertion of
ipg_stop_ack:
• If a serial transfer is in progress in one of the SPI modes the QuadSPI waits until it reaches the
frame boundary before asserting ipg_stop_ack.
• If a SFM command is currently executed in SFM mode the assertion of the ipg_stop_ack is
postponed until this command is finished.
While the clocks are shut off, the QuadSPI memory-mapped logic is not accessible. The states of the
interrupt and DMA request signals cannot be changed while in Stop mode.
Note that the following actions are illegal in SFM mode during the time starting with raising the request
to enter Stop mode and ending with leaving the Stop mode:
• Issue a new SFM command
• Issue a new AHB request
30.5.4.1 Module Disable mode
Module Disable mode is a block-specific mode that the QuadSPI can enter to save power. Host software
can initiate the Module Disable mode by writing a 1 to the MDIS bit in the QSPI_MCR.
When a request is encountered to enter the Module Disable mode the QuadSPI negates ipg_enable_clk
when it is ready to enter the Module Disable mode. Depending from the mode of operation the following
conditions must be met for the negation of ipg_enable_clk:
• If a serial transfer is in progress in one of the SPI modes the QuadSPI waits until it reaches the
frame boundary before negating ipg_enable_clk.
• If a SFM command is currently executed in SFM mode the negation of ipg_enable_clk is
postponed until this command is finished.
Note that there is only a limited possibility to read back whether the QuadSPI block is waiting for the
completion of these conditions or whether it has already negated the ipg_enable_clk. The host software
can read the QSPI_SFMSR[BUSY] bit to check for pending execution of a SFM command, but there is
no possibility to check pending DMA or CPU read requests on the AHB Buffer.
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