NXP Semiconductors MPC5606S - Timer Control (TCTRL) Register

Periodic Interrupt Timer (PIT)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 977
27.3.2.4 Timer Control (TCTRL) register
The Timer Control (TCTRL) register contains the control bits for each timer.
27.3.2.5 Timer Flag (TFLG) register
The Timer Flag (TFLG) register holds the PIT interrupt flags.
Table 27-5. CVAL field descriptions
Field Description
TVLn Current Timer Value. These bits represent the current timer value. Note that the timer uses a
downcounter.
NOTE: The timer values will be frozen in Debug mode if the FRZ bit is set in the PIT Module Control
Register (see Figure 27-2)
Offset: Channel_base + 0x08 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TIE TEN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 27-5. Timer Control (TCTRL) register
Table 27-6. TCTRL field descriptions
Field Description
TIE Timer Interrupt Enable Bit.
0 Interrupt requests from Timer x are disabled
1 Interrupt will be requested whenever TIF is set
When an interrupt is pending (TIF set), enabling the interrupt will immediately cause an interrupt
event. To avoid this, the associated TIF flag must be cleared first.
TEN Timer Enable Bit.
0 Timer will be disabled
1 Timer will be active