Overview
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 53
bypassing the interrupt controller completely. Once the edge detection logic is programmed, it cannot be
disabled, except by reset. The NMI is, as the name suggests, completely un-maskable and when asserted
will always result in the immediate execution of the respective interrupt service routine. The NMI is not
guaranteed to be recoverable.
The CPU core has an additional Wait for Interrupt instruction that is used in conjunction with low-power
Stop mode. When Low-power Stop mode is selected, this instruction is executed to allow the system clock
to be stopped. An external interrupt source or the system wakeup timer is used to restart the system clock
and allow the CPU to service the interrupt.
Additional features include:
• Load/store unit
— 1-cycle load latency
— Misaligned access support
— No load-to-use pipeline bubbles
• Thirty-two 32-bit general purpose registers (GPRs)
• Separate instruction bus and load/store bus Harvard architecture
• Reservation instructions for implementing read-modify-write constructs
• Multi-cycle divide (divw) and load multiple (lmw) store multiple (smw) multiple class
instructions; can be interrupted to prevent increases in interrupt latency
• Extensive system development support through Nexus debug port
1.5.3 Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and
four slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave port, but one
of those transfers must be an instruction fetch from internal flash. If a slave port is simultaneously
requested by more than one master port, arbitration logic selects the higher priority master and grants it
ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority
master completes its transactions. Requesting masters having equal priority are granted access to a slave
port in round-robin fashion, based upon the ID of the last master to be granted access.
The crossbar provides the following features:
• Four master ports:
— e200z0h core instruction port
— e200z0h core complex load/store data port
— eDMA controller
— Display control unit
• Four slave ports:
— One flash port dedicated to the CPU
— Platform SRAM
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