NXP Semiconductors MPC5606S - Instruction Code Register (QSPI_ICR)

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1019
30.4.3.12 Instruction Code Register (QSPI_ICR)
The Instruction Code Register consists of the generic instruction code (IC) and an additional parameter
section (ICO). This contains additional options to parameterize the command as shown in Table 30-53.
If the IC field is written successfully—while the module is in Serial Flash mode and not busy—a new
command to the external serial flash device is started with that instruction code if this code is supported
by the module (see 30.7.1, Supported Instruction Codes in Winbond Devices).
The QSPI_ICR register is writable only in SFM mode.
Refer to Section 30.5.3.1, Issuing SFM Commands, for further details about the triggering of IP
Commands.
Address: QSPI_BASE + 0x100 Write: QSPI_SFMSR[IP_ACC] = 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SFADR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SFADR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-11. Serial Flash Address Register (QSPI_SFAR)
Table 30-24. QSPI_SFAR field descriptions
Field Description
SFADR Serial Flash Address, register content is used as address for all following IP Commands.