Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1064 Freescale Semiconductor
account not only the data rate provided by the serial flash but also the data rate of the AHB bus and the
performance of the DMA controller in reading data from the RX Buffer.
Depending from the clock frequency of the serial flash and from the clock frequency of the AHB bus it
may be that the serial flash read bandwidth is higher than the data are read out from the RX Buffer. If this
is the case the RX Buffer will be filled up continuously. The limiting factor is the number of bytes read out
from the serial flash, this read out must be finished before the RX Buffer is forced in the overrun condition.
This is illustrated in the examples below, the common setup for both of them is:
• AHB bus clock frequency 64 MHz
• RX Buffer read rate (two successive reads of the RX Buffer by DMA) 11 cycles
• Serial flash clock identical to AHB bus clock (64 MHz)
• No other DMA transfers slowing down the DMA channel assigned to the QuadSPI module
• 14 out of the 15 entries in the RX Buffer available for actual buffering
From Table 30-51 above it can be seen that despite the assumed undisturbed DMA transfers the transfer
length is limited to e.g. 16 words when reading the serial flash in Quad I/O mode. Careful analysis of the
DMA usage in the entire device containing the QuadSPI module is required to avoid RX Buffer overrun.
It is highly recommended to enable the interrupt associated with the QSPI_SFMFR[RBOF] to notice this
overrun condition.
When running the serial flash in Dual I/O mode the RX Buffer read rate is higher than the data from the
serial flash are written to the RX Buffer so the RX Buffer overrun can only happen if the DMA channel of
the QuadSPI is stalled for more than (16
* 14) = 224 cycles in sequence or if the average DMA transfer
rate is lengthened from 11 cycles to more than 16 cycles.
30.7 Serial Flash Devices
Currently flash memory devices with serial flash bus are developed by several vendors. Most standard
commands currently have the same instruction code for all vendors, some commands are however unique
for one vendor. The currently supported list of instruction codes and the required instruction code options
are provided in this chapter.
Table 30-51. DMA example in SFM mode
Fast read dual I/O Fast read quad I/O
Number of cycles to read 4 bytes from serial flash 16 8
Number of cycles to transfer 4 bytes via DMA 11
Number of bytes available for buffering (14 * 4) 56
Number of cycles to fill up available buffer N/a 3 * (14 * 4) = 168
Number of 4 byte words read from serial flash in that time N/a 168 / 8 = 21
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