System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
1188 Freescale Semiconductor
37.4.1 Detailed signal descriptions
37.4.1.1 General-purpose I/O pins (GPIO[0:132])
The GPIO pins provide general-purpose input and output function. The GPIO pins are generally
multiplexed with other I/O pin functions. Each GPIO input and output is separately controlled by an input
(GPDIn_n) or output (GPDOn_n) register.
37.4.1.2 External interrupt request input pins (EIRQ[0:13])
1
The EIRQ[0:13] are connected to the SIU inputs. Rising or falling edge events are enabled by setting the
corresponding bits in the SIU_IREER or the SIU_IFEER register.
37.5 Memory map and register description
This section provides a detailed description of all registers accessible in the SIUL module.
37.5.1 SIUL memory map
Table 37-2 gives an overview on the SIUL registers implemented.
IRQ_1 EIF[8] PCR[80] PF[10] x x x
EIF[9] PCR[86] PG[0] x x x
EIF[10] PCR[87] PG[1] x x x
EIF[11] PCR[98] PG[12] x x x
EIF[12] PCR[131] PK[10] — x x
EIF[13] PCR[132] PK[11] — x x
1. EIRQ[0:11] in the 144-pin LQFP; EIRQ[0:13] in all other packages
Table 37-2. SIUL memory map
Address Name Description
Size
(bits)
Location
Base (0xC3F9_0000) — Reserved — —
Base + 0x0004 MIDR1 MCU ID Register #1 32-bit on page
1190
Base + 0x0008 MIDR2 MCU ID Register #2 32-bit on page
1191
Base + (0x000C–0x0013) — Reserved — —
Table 37-1. SIUL signal properties (continued)
External IRQ Flag PCR Port
Package
144 176 208
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