Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 601
• In case of a failing system locations (configurations, device options, redundancy, EmbAlgo
firmware), the initialization phase is interrupted and a Fatal Error is flagged.
• In case of failing user locations (protections, censorship, BIU, etc.), the Volatile Registers are filled
with all 1s and the flash memory initialization ends setting low the PEG bit of MCR.
In this section, the following abbreviations are used
17.3.6.1 Module Configuration Register (MCR)
The Module Configuration Register is used to enable and monitor all the Modify Operations of the flash
module.
Table 17-41. Abbreviations
Case Abbreviation Description
read/write rw The software can read and write to these bits.
read/clear rc The software can read and clear to these bits.
read-only r The software can only read these bits.
write-only w The software should only write to these bits.
Address Offset: 0x0000 Reset value: 0x06600600
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EDC 0 0 0 0
SIZE
2
SIZE
1
SIZE
0
0 LAS2 LAS1 LAS0 0 0 0 MAS
rc/0 r/0 r/0 r/0 r/0 r/1 r/1 r/0 r/0 r/1 r/1 r/0 r/0 r/0 r/0 r/0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EER RWE 0 0 PEAS
DON
E
PEG 0 0 0 0 PGM PSUS ERS ESUS EHV
rc/0 rc/0 r/0 r/0 r/0 r/1 r/1 r/0 r/0 r/0 r/0 rw/0 rw/0 rw/0 rw/0 rw/0
Figure 17-27. Module Configuration Register (MCR)
Table 17-42. MCR field descriptions
Field Description
0 EDC: ECC Data Correction (Read/Clear)
EDC provides information on previous reads. If a ECC Single Error detection and correction occurred, the
EDC bit will be set to 1. This bit must then be cleared, or a reset must occur before this bit will return to a
0 state. This bit may not be set to 1 by the user.
In the event of a ECC Double Error detection, this bit will not be set.
If EDC is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of
EDC) were not corrected through ECC.
Since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. A write of 0 will
have no effect.
The function of this bit is SoC dependent and it can be configured to be disabled.
0: Reads are occurring normally.
1: An ECC Single Error occurred and was corrected during a previous read.
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