Stepper Motor Controller (SMC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1127
35.3.2.2 Motor Controller Control Register 1 (MCCTL1)
This register controls the behavior of the analog section of the SMC as well as the interrupt enables.
Offset Module Base + 0x0001
0 1 2 3 4 5 6 7
R
RECIRC
0 0 0 0 0 0
MCTOIE
W
Reset 0 0 0 0 0 0 0 0
Figure 35-3. Motor Controller Control Register 1 (MCCTL1)
Table 35-5. MCCTL1 field descriptions
Field Description
RECIRC Recirculation in (Dual) Full H-Bridge Mode (refer to Section 35.4.1.3.3, Recirculation Bit
(MCCTL1[RECIRC])) — RECIRC only affects the outputs in (dual) full H-bridge modes. In half
H-bridge mode, the PWM output is always active low. RECIRC = 1 will also invert the effect of the
MCDCx[SIGN] bits (refer to Section 35.4.1.3.2, Sign Bit (MCDCx[SIGN])) in (dual) full H-bridge
modes. RECIRC must be changed only while no PWM channel is operating in (dual) full H-bridge
mode; otherwise, erroneous output pattern may occur.
0 Recirculation on the high side transistors. Active state for PWM output is logic low, the static
channel will output logic high.
1 Recirculation on the low side transistors. Active state for PWM output is logic high, the static
channel will output logic low.
MCTOIE Motor Controller Timer Counter Overflow Interrupt Enable
0 Interrupt disabled.
1 Interrupt enabled. An interrupt will be generated when the motor controller timer counter overflow
interrupt flag (MCCTL0[MCTOIF]) is set.
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