Peripheral Bridge (PBRIDGE)
MPC5606S Microcontroller Reference Manual, Rev. 7
982 Freescale Semiconductor
28.2.1.2 Read Cycles
Two-clock read accesses are possible with the PBRIDGE when the requested access size is 32-bits or
smaller, and is not misaligned across a 32-bit boundary.
28.2.1.3 Write Cycles
Three-clock write accesses are possible with the PBRIDGE when the requested access size is 32-bits or
smaller. Misaligned writes that cross a 32-bit boundary are not supported.
28.2.2 General Operation
Slave peripherals are modules that contain readable/writable control and status registers. The system bus
master reads and writes these registers through the PBRIDGE. The PBRIDGE generates module enables,
the module address, transfer attributes, byte enables, and write data as inputs to the slave peripherals. The
PBRIDGE captures read data from the slave interface and drives it on the system bus.
The PBRIDGE occupies a 64 MB portion of the address space. The register maps of the slave peripherals
are located on 16-KB boundaries. Each slave peripheral is allocated one 16-KB block of the memory map,
and is activated by one of the module enables from the PBRIDGE.
The PBRIDGE is responsible for indicating to slave peripherals if an access is in supervisor or user mode.
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