NXP Semiconductors MPC5606S - Register Map

Register Map
MPC5606S Microcontroller Reference Manual, Rev. 7
1286 Freescale Semiconductor
Reserved — — Base +
(0x001C–0x036F)
Clock Generation Module (MC_CGM) Section 8.4.3, Memory map and register definition 0xC3FE_0370
Output Clock Enable Register CGM_OC_EN 32-bit Base + 0x0000
Output Clock Division Select Register CGM_OCDS_SC 32-bit Base + 0x0004
System Clock Select Status Register CGM_SC_SS 32-bit Base + 0x0008
System Clock Divider Configuration Registers CGM_SC_DC0 8-bit Base + 0x000C
System Clock Divider Configuration Registers CGM_SC_DC1 8-bit Base + 0x000D
System Clock Divider Configuration Registers CGM_SC_DC2 8-bit Base + 0x000E
System Clock Divider Configuration Registers CGM_SC_DC3 8-bit Base + 0x000F
Reset Generation Module (MC_RGM) Section 31.3, Memory map and register definition 0xC3FE_4000
Functional Event Status RGM_FES 16-bit Base + 0x0000
Destructive Event Status RGM_DES 16-bit Base + 0x0002
Functional Event Reset Disable RGM_FERD 16-bit Base + 0x0004
Destructive Event Reset Disable RGM_DERD 16-bit Base + 0x0006
Reserved — — Base +
(0x0008–0x000F)
Functional Event Alternate Request RGM_FEAR 16-bit Base + 0x0010
Destructive Event Alternate Request RGM_DEAR 16-bit Base + 0x0012
Reserved — — Base +
(0x0014–0x0017)
Functional Event Short Sequence RGM_FESS 16-bit Base + 0x0018
Standby reset sequence RGM_STDBY 16-bit Base + 0x001A
Functional Bidirectional Reset Enable RGM_FBRE 16-bit Base + 0x001C
Reserved — — Base +
(0x001E–0x3FFF
)
Power Control Unit (MC_PCU) Section 29.3, Memory map and register definition 0xC3FE_8000
Power domain #0 configuration register PCONF0 32-bit Base + 0x0000
Power domain #1 configuration register PCONF1 32-bit Base + 0x0004
Power domain #1 configuration register PCONF2 32-bit Base + 0x0008
Reserved — — Base +
(0x000C–0x003F)
Power Domain Status Register PSTAT 32-bit Base + 0x0040
Table B-2. Detailed register map (continued)
Register description Register Name
Used
Size
Address