e200z0h Core
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 461
Chapter 14
e200z0h Core
14.1 Overview
The e200 processor family is a set of CPU cores that implement low-cost versions of the
Power Architecture
®
Book E architecture. e200 processors are designed for deeply embedded control
applications which require low cost solutions rather than maximum performance.
The processors integrate an integer execution unit, branch control unit, instruction fetch and load/store
units, and a multi-ported register file capable of sustaining three read and two write operations per clock.
Most integer instructions execute in a single clock cycle. Branch target prefetching is performed by the
branch unit to allow single-cycle branches in some cases.
The e200z0h core is a single-issue, 32-bit PowerPC Book E VLE-only design with 32-bit general purpose
registers (GPRs). All arithmetic instructions that execute in the core operate on data in the general purpose
registers (GPRs).
Instead of the base PowerPC Book E instruction set support, the e200z0h core only implements the VLE
(variable-length encoding) APU, providing improved code density. The VLE APU is further documented
in the PowerPC™ VLE APU Definition, a separate document.
14.2 Features
The following is a list of some of the key features of the e200z0h core:
• 32-bit Power Architecture Book E programmer’s model
• Single issue, 32-bit CPU
• Implements the VLE APU for reduced code footprint
• In-order execution and retirement
• Precise exception handling
• Branch processing unit
— Dedicated branch address calculation adder
— Branch acceleration using Branch Target Buffer (BTB)
• Supports independent instruction and data accesses to different memory subsystems, such as
SRAM and flash memory via independent Instruction and Data bus interface units (BIUs).
• Load/store unit
— 1 cycle load latency
— Fully pipelined
— Big- and Little-endian support
— Misaligned access support
— Zero load-to-use pipeline bubbles for aligned transfers
• Power management
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