Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
650 Freescale Semiconductor
17.4.4.3 Read cycles—buffer hit
Single cycle read responses to the AHB are possible with the PFLASH2P_LCA when the requested read
access was previously loaded into one of the page buffers associated with banks 0 and 2. In these “buffer
hit” cases, read data is returned to the AHB data phase with a zero wait-state response.
Likewise, the bank1 logic includes 128-bit temporary holding registers (one per AHB port) and sequential
accesses which “hit” in these registers are also serviced with a zero wait-state response.
17.4.4.4 Write cycles
In a write cycle, address, write data, and control signals are launched off the same edge of hclk at the
completion of the first AHB data phase cycle. Write cycles to the flash array are initiated by driving a valid
access address on bkn_fl_addr[23:0], driving write data on bkn_fl_wdata[63:0], and asserting
bkn_fl_wr_en. Again, the controller drives the address and control information for the required setup time
before the rising edge of hclk, and provides the required amount of hold time. The PFLASH2P_LCA then
waits for the appropriate number of write wait-states before terminating the write operation. On the cycle
following the programmed wait state value, the PFLASH2P_LCA asserts hready_out to indicate to the
AHB port that the cycle has terminated.
17.4.4.5 Error termination
The PFLASH2P_LCA follows the standard procedure when an AHB bus cycle is terminated with an
ERROR response. First, the PFLASH2P_LCA asserts hresp[0] and negates hready_out to signal an error
has occurred. On the following clock cycle, the PFLASH2P_LCA asserts hready_out and holds both
hresp[0] and hready_out asserted until hready_in is asserted.
The first case that can cause an error response to the AHB is when an access is attempted by an AHB
master whose corresponding Read Access Control or Write Access Control settings do not allow the
access, thus causing a protection violation. In this case, the PFLASH2P_LCA does not initiate a flash array
access.
The second case that can cause an error response to the AHB is when an access is performed to the flash
array and is terminated with a flash error response. See
Section 17.4.4.7, Flash error response operation.
This may occur for either a read or a write operation.
The third case that can cause an error response to the AHB is when a write access is attempted to the flash
array and is disallowed by the state of the bkn_fl_ary_access control input. This case is similar to case 1.
A fourth case involves an attempted read access while the flash array is busy doing a write (program) or
erase operation if the appropriate read-while-write control field is programmed for this response. The 3-bit
read-while-write control allows for immediate error termination of an attempted read, or various
combinations involving stalls with optional notification interrupts while program/erase operations are
occurring.
The PFLASH2P_LCA can also terminate the current AHB access if hready_in is asserted before the end
of the current bus access. While this circumstance should not occur, this does not result in an error
condition being reported, as this behavior is initiated by the AHB master. In this circumstance, the
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