NXP Semiconductors MPC5606S - Parallel GPIO Pad Data out Registers (PGPDO0-PGPDO4)

System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1203
37.5.3.12 Parallel GPIO Pad Data Out Registers (PGPDO0–PGPDO4)
These registers are used to set or clear the respective pads of the device.
Address: Base + 0x0800–0x0884 (34 registers) Access: User read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0
PDI
[0]
0 0 0 0 0 0 0
PDI
[1]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0
PDI
[2]
0 0 0 0 0 0 0
PDI
[3]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 37-14. Port GPIO Pad Data Input register 0–3 (GPDI0_3)
Table 37-14. GPDI field descriptions
Field Description
PDI[x] Pad Data In
This bit stores the value of the external GPIO pad associated with this register.
0 The value of the data in signal for the corresponding GPIO pad is logic low
1 The value of the data in signal for the corresponding GPIO pad is logic high
Address: Base + 0x0C00–0x0C10 (5 registers) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
PPDO[x][15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PPDO[x+1][15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 37-15. Parallel GPIO Pad Data Out Register (PGPDO0)