NXP Semiconductors MPC5606S - 30.6.5.1 Address Calculation for the First-In Entry and Last-In Entry in the TX FIFO

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1060 Freescale Semiconductor
Figure 30-35. TX FIFO Pointers and Counter
30.6.5.1 Address Calculation for the First-in Entry and Last-in Entry in the TX
FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following equation:
Eqn. 30-7
The memory address of the last-in entry in the TX FIFO is computed by the following equation:
Eqn. 30-8
TX FIFO Base—Base address of TX FIFO
TXCTR—TX FIFO Counter
TXNXTPTR—Transmit Next Pointer
TX FIFO Depth—implementation specific
30.6.5.2 Address Calculation for the First-in Entry and Last-in Entry in the RX
FIFO
The memory address of the first-in entry in the RX FIFO is computed by the following equation:
Eqn. 30-9
The memory address of the last-in entry in the RX FIFO is computed by the following equation:
Eqn. 30-10
RX FIFO Base—Base address of RX FIFO
-
-
Entry A (first in)
Entry B
Entry C
Entry D (last in)
-
-
Push TX FIFO Register
Transmit Next
Data Pointer
Shift Register
SO
+1
-1
TX FIFO Counter
TX FIFO Base
First-in Entry Address TX FIFO Base 4 TXNXTPTR+=
Last-in Entry address TX FIFO Base 4 modulo TX FIFO depth TXCTR TXNXTPTR 1–++=
First-in Entry Address RX FIFO Base 4 POPNXTPTR+=
Last-in Entry address RX FIFO Base 4 modulo RX FIFO depth RXCTR POPNXTPTR 1–++=