System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
1190 Freescale Semiconductor
NOTE
A transfer error will be issued when trying to access reserved register space.
37.5.2 Register protection
The individual registers of SIUL are protected from accidental writes. The following registers are
protected:
•IRER (Interrupt Request Enable Register)
• IREER (Interrupt Rising-Edge Event Enable Register)
• IFEER (Interrupt Falling-Edge Event Enable Register)
•IFER (Interrupt Filter Enable Register), entire PortA, PortB[0:3] and PortC[2:15]
• PSMI[n] (Pad Selection for Multiplexed Inputs)
•IFMC[n] (Interrupt Filter Maximum Counter)
•IFPC (Interrupt Filter Clock Prescaler)
Refer to Appendix A, Registers Under Protection, for details.
37.5.3 Register description
This section describes in address order all the SIUL registers. Each description includes a standard register
diagram. Details of register bit and field function follow the register diagrams, in bit order. The numbering
convention of register is MSB=0, however the numbering of internal field is LSB=0, e.g. PARTNUM[5]
= MIDR1[10].
Figure 37-2. Key to Register Fields
37.5.3.1 MCU ID Register #1 (MIDR1)
This register holds identification information about the device.
Base + 0x1080 IFCP Interrupt Filter Clock Prescaler Register 32-bit on page
1207
Base + (0x1084–0x3FFF) — Reserved — —
1
Not all port pins are available in all packages.
Always
1
Always
0 R/W
BIT
Read -
BIT
Write - Write 1
BIT
Self -
0
N/A
reads 1 reads 0 bit only bit only bit BIT to clear w1c clear bit BIT
Table 37-2. SIUL memory map (continued)
Address Name Description
Size
(bits)
Location
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