NXP Semiconductors MPC5606S - Chapter 29; Power Domain #1 Configuration Register (PCU_PCONF1)

Power Control Unit (MC_PCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
988 Freescale Semiconductor
29.3.2.2 Power Domain #1 Configuration Register (PCU_PCONF1)
This register defines for power domain #1 whether it is on or off in each device mode. The bit field
description is the same as in Table 29-3. As the platform, clock generation, and mode control reside in
power domain #1, this power domain is only powered down during the Standby mode. Therefore, none of
the bits is programmable. This register is available for completeness reasons.
The difference between PCU_PCONF0 and PCU_PCONF1 is the reset value of the STBY0 bit: During
the Standby mode, power domain #1 is disconnected from the power supply, and therefore
PCU_PCONF1.STBY0 is always 0. Power domain #0 is always on, and therefore PCU_PCONF0.STBY0
is 1.
For further details about Standby mode, please refer to Section 29.4.4.2, Standby mode transition.
29.3.2.3 Power Domain #2 Configuration Register (PCU_PCONF2)
This register defines for power domain #2 whether it is on or off in each device mode. The bit field
description is the same as in
Table 29-3.
Address 0xC3FE_8004 Access: Supervisor read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0
STBY0
0 0
STOP
0
HALT
RUN3 RUN2 RUN1 RUN0
DRUN
SAFE
TEST
RST
W
Reset 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1
Figure 29-3. Power Domain #1 Configuration Register (PCU_PCONF1)
Address 0xC3FE_8008 Access: Supervisor read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0
STBY0
0 0
STOP
0
HALT
RUN3 RUN2 RUN1 RUN0
DRUN
SAFE
TEST
RST
W
Reset 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1
Figure 29-4. Power Domain #2 Configuration Register (PCU_PCONF2)