NXP Semiconductors MPC5606S - Fixed Group Arbitration, Round-Robin Channel Arbitration

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 515
prevent the servicing of other channels in its group. Any DMA requests that are not serviced are simply
lost, but at least one channel will be serviced.
This scenario ensures that all channels will be guaranteed service at some point, regardless of the request
rates. However, the potential latency could be quite high.
All channels are treated equally. Priority levels are not used in round robin/round robin mode.
15.5.3.4 Fixed group arbitration, round-robin channel arbitration
The highest priority group with a request will be serviced. Lower priority groups will be serviced if no
pending requests exist in the higher priority groups.
Within each group, channels are serviced starting with the highest channel number and rotating through to
the lowest channel number without regard to the channel priority levels assigned within the group.
This scenario could cause the same bandwidth consumption problem as indicated in Section 15.5.3.1,
Fixed group arbitration, fixed channel arbitration, but all the channels in the highest priority group will be
serviced.
Service latency will be short on the highest priority group, but can become much longer as the group
priority decreases.
15.5.4 DMA transfer
15.5.4.1 Single request
To perform a simply transfer of ‘n’ bytes of data with one activation, set the major loop to one (TCD.citer
= TCD.biter = 1). The data transfer will begin after the channel service request is acknowledged and the
channel is selected to execute. Once the transfer is complete, the TCD.done bit will be set and an interrupt
will be generated if properly enabled.
For example, the following TCD entry is configured to transfer 16 bytes of data. The DMA is programmed
for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide
memory port located at 0x1000. The destination memory has a word wide port located at 0x2000. The
address offsets are programmed in increments to match the size of the transfer; one byte for the source and
four bytes for the destination. The final source and destination addresses are adjusted to return to their
beginning values.
TCD.citer = TCD.biter = 1
TCD.nbytes = 16
TCD.saddr = 0x1000
TCD.soff = 1
TCD.ssize = 0
TCD.slast = -16