NXP Semiconductors MPC5606S - Register Description

Wakeup Unit (WKPU)
MPC5606S Microcontroller Reference Manual, Rev. 7
1240 Freescale Semiconductor
NOTE
Reserved registers will read as 0, writes will have no effect. If supported and
enabled by the SoC, a transfer error will be issued when trying to access
completely reserved register space.
41.4.2 Register description
This section describes in address order all the Wakeup Unit registers. Each description includes a standard
register diagram with an associated figure number. Details of register bit and field function follow the
register diagrams, in bit order. The numbering convention of register is MSB = 0, however the numbering
of internal field is LSB = 0. For example, EIF[5] = WISR[26].
41.4.2.1 NMI Status Flag Register (NSR)
This register holds the non-maskable interrupt status flags.
0x0020–0x0027 Reserved
0x0028 Wakeup/Interrupt Rising-Edge Event Enable
Register
WIREER 32 32
0x002C Wakeup/Interrupt Falling-Edge Event Enable
Register
WIFEER 32 32
0x0030 Wakeup/Interrupt Filter Enable Register WIFER 32 32
0x0034 Wakeup/Interrupt Pullup Enable Register WIPUER 32 32
0x0038–0x03FFF Reserved
Address: Base + 0x0000 Access: User read/write (write 1 to clear)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R NIF NOVF 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 41-2. NMI Status Flag Register (NSR)
Table 41-2. WKPU memory map (continued)
Address offset Use Abbreviation Size
Supported
access sizes