System Integration Unit Lite (SIUL)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1193
37.5.3.3 Interrupt Status Flag Register (ISR)
This register holds the external interrupt flags.
37.5.3.4 Interrupt Request Enable Register (IRER)
This register is used to enable the external interrupt messaging to the interrupt controller.
Address: Base + 0x0014 Access: User read/write (write 1 to clear)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EIF[13:0]
1
1
EIF[11:0] is valid in the 144-pin LQFP.
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 37-5. Interrupt Status Flag Register (ISR)
Table 37-5. ISR field descriptions
Field Description
EIF[x] External Interrupt Status Flag x
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRER[x]), EIF[x]
causes an interrupt request.
0 No interrupt event has occurred on the pad
1 An interrupt event as defined by IREER[x] and IFEER[x] has occurred
Address: Base + 0x0018 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IRE[13:0]
1
1
IRE[11:0] is valid in the 144-pin LQFP.
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 37-6. Interrupt Request Enable Register (IRER)
Table 37-6. IRER field descriptions
Field Description
IRE[x] External Interrupt Request Enable x
0 Interrupt requests from the corresponding EIF[x] bit are disabled
1 A set EIF[x] bit causes an interrupt request
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