NXP Semiconductors MPC5606S - Debug Support

Real-Time Clock (RTC/API)
MPC5606S Microcontroller Reference Manual, Rev. 7
1098 Freescale Semiconductor
32.5 Debug support
To simplify software development it is possible to temporarily suspend the RTC counter while the MCU
is stopped by a debugger. While the MCU is running the RTC counter runs normally. This feature is
enabled by setting the RTCC[FRZ] bit and is only available when the CPU has debug mode active (see the
CPU reference manual for more information on debug mode and support).
32.6 Register descriptions
32.6.1 RTC Supervisor Control Register (RTCSUPV)
The RTCSUPV register contains the SUPV bit which determines whether other registers are accessible in
supervisor mode or user mode.
NOTE
RTCSUPV register is accessible only in supervisor mode.
Figure 32-3. RTC Supervisor Control Register (RTCSUPV)
Offset: RTC_BASE + 0x0000
0 1 2 3 4 5 6 7 8 9 1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
R SUP
V
W
POR 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 32-1. RTCSUPV Register Bit/field descriptions
Field Description
0
SUPV
RTC Supervisor Bit
0 All registers are accessible in both user as well as supervisor mode.
1 All other registers are accessible in supervisor mode only.