NXP Semiconductors MPC5606S - Functional Description

Safety
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 127
4.2.6 Functional description
The SWT is a 32-bit timer designed to enable the system to recover in situations such as software getting
trapped in a loop or if a bus transaction fails to terminate. It includes a a control register (SWT_CR), an
interrupt register (SWT_IR), timeout register (SWT_TO), a window register (SWT_WN), a service
register (SWT_SR) and a counter output register (SWT_CO).
The SWT_CR includes bits to enable the timer, set configuration options and lock configuration of the
module. The watchdog is enabled by setting the SWT_CR[WEN] bit. The reset value of the
SWT_CR[WEN] bit is 0 when exiting Reset mode if the flash user option bit 31 (WATCHDOG_EN) is
`0'. If the reset value of WATCHDOG_EN is 1, the SWT_CR[WEN] bit is set and the watchdog starts
operation automatically after reset is released.
The SWT_TO register holds the watchdog timeout period in clock cycles unless the value is less than
0x100, in which case the timeout period is set to 0x100. This timeout period is loaded into an internal
32-bit down counter when the SWT is enabled and each time a valid service sequence is written. The
SWT_CR[CSL] bit selects which clock (system or oscillator) is used to drive the down counter.
NOTE
The initial value of the SWT timer counter may not be correct when starting
after reset. Therefore, it is important to clear the SWT as soon as possible
after reset to minimize an unexpected SWT event. The SWT will behave
correctly once it has been cleared at least once.
The configuration of the SWT can be locked through use of either a soft lock or a hard lock. In either case,
when locked the SWT_CR, SWT_TO and SWT_WN registers are read only. The hard lock is enabled by
setting the SWT_CR[HLK] bit, which can only be cleared by a reset. The soft lock is enabled by setting
the SWT_CR[SLK] bit and is cleared by writing the unlock sequence to the service register. The unlock
sequence is a write of 0xC520 followed by a write of 0xD928 to the SWT_SR[WSC] field. There is no
timing requirement between the two writes. The unlock sequence logic ignores service sequence writes
and recognizes the 0xC520, 0xD928 sequence regardless of previous writes. The unlock sequence can be
written at any time and does not require the SWT_CR[WEN] bit to be set.
When enabled, the SWT requires periodic execution of the watchdog servicing sequence. The service
sequence is a write of 0xA602 followed by a write of 0xB480 to the SWT_SR[WSC] field. Writing the
service sequence loads the internal down counter with the timeout period. There is no timing requirement
between the two writes. The service sequence logic ignores unlock sequence writes and recognizes the
0xA602, 0xB480 sequence regardless of previous writes. Accesses to SWT registers occur with no
peripheral bus wait states. (The peripheral bus bridge may add one or more system wait states.) However,
due to synchronization logic in the SWT design, recognition of the service sequence or configuration
changes may require up to three system plus seven counter clock cycles.
If window mode is enabled (SWT_CR[WND] bit is set), the service sequence must be performed in the
last part of the timeout period defined by the window register. The window is open when the down counter
is less than the value in the SWT_WN register. Outside of this window, service sequence writes are invalid
accesses and generate a bus error or reset depending on the value of the SWT_CR[RIA] bit. For example,