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NXP Semiconductors MPC5606S User Manual

NXP Semiconductors MPC5606S
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FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 687
18.3.4.4 Rx Global Mask (RXGMASK)
This register is provided for legacy support and for low-cost MCUs that do not have the individual masking
per Message Buffer feature. For MCUs supporting individual masks per MB, setting the BCC bit in MCR
causes the RXGMASK Register to have no effect on the module operation. For MCUs not supporting
individual masks per MB, this register is always effective.
RXGMASK is used as acceptance mask for all Rx MBs, excluding MBs 1415, which have individual
mask registers. When the FEN bit in MCR is set (FIFO enabled), the RXGMASK also applies to all
elements of the ID filter table, except elements 6-7, which have individual masks.
The contents of this register must be programmed while the module is in Freeze mode, and must not be
modified when the module is transmitting or receiving frames.
When used with the FEN bit set, there is a misalignment between the position of the ID field in the Rx MB
and in RXIDA, RXIDB, and RXIDC fields of the ID tables. In fact, the RXIDA filter in the ID tables is
shifted one bit to the left from the Rx MBs ID position as shown below:
Rx MB ID = bits 3–31 of ID word corresponding to message ID bits 0–28
RXIDA = bits 2–30 of ID Table corresponding to message ID bits 0–28
Note that for the mask bits, one-to-one correspondence occurs with the filter bits, not with the incoming
message ID bits.
This leads the RXGMASK to affect Rx MB and Rx FIFO filtering in different ways.
For example, if the user intends to mask out bit 24 of the ID filter of Message Buffers, then the RXGMASK
will be configured as 0xFFFF_FFEF. As result, bit 24 of the ID field of the incoming message will be
ignored during the filtering process for Message Buffers. This very same configuration of RXGMASK
would lead bit 24 of RXIDA to be a don’t-care bit, and thus bit 25 of the ID field of the incoming message
would be ignored during the filtering process for the Rx FIFO.
Similarly, both RXIDB and RXIDC filters have multiple misalignments with regards to position of the ID
field in Rx MBs, which can lead to erroneous masking during filtering process for either Rx FIFO or MBs.
Address: Base + 0x0010 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 18-8. Rx Global Mask Register (RXGMASK)

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NXP Semiconductors MPC5606S Specifications

General IconGeneral
BrandNXP Semiconductors
ModelMPC5606S
CategoryMicrocontrollers
LanguageEnglish

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