NXP Semiconductors MPC5606S - Effect of Freeze on the GCP

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
274 Freescale Semiconductor
9.5.3.1 Effect of Freeze on the GCP
When the FRZ bit in the EMIOSMCR register is set and the module is in debug mode, the operation of the
GCP submodule is not affected. There is no freeze function in this submodule.
9.6 Initialization/application information
On resetting the eMIOS200, the Unified Channels enter GPIO input mode.
9.6.1 Considerations
Before changing an operating mode, the UC must be programmed to GPIO mode and the EMIOSA[n] and
EMIOSB[n] registers must be updated with the correct values for the next operating mode. Then the
EMIOSC[n] register can be written with the new operating mode. If a UC is changed from one mode to
another without performing this procedure, the first operation cycle of the selected time base can be
random, that is, matches can occur in random time if the contents of EMIOSA[n] or EMIOSB[n] were not
updated with the correct value before the time base matches the previous contents of EMIOSA[n] or
EMIOSB[n].
When interrupts are enabled, the software must clear the FLAG bits before exiting the interrupt service
routine.
9.6.2 Application information
Correlated output signals can be generated by all output operation modes. Bits OU[n] of the
EMIOSOUDIS register can be used to control the update of these output signals.
In order to guarantee that the internal counters of correlated channels are incremented in the same clock
cycle, the internal prescalers must be set up before enabling the global prescaler. If the internal prescalers
are set after enabling the global prescaler, the internal counters may increment in the same ratio, but at a
different clock cycle.
It is recommended to drive Output Disable Input signals with the emios_flag_out signals of some UCs
running in SAIC mode. When an output disable condition happens, the software interrupt routine must
service the output channels before servicing the channels running SAIC. This procedure avoids glitches in
the output pins.
9.6.2.1 Time Base Generation
For the OPWFM with internal clock source operation mode, the internal counter rate can be modified by
configuring the clock prescaler ratio.
Figure 9-40 shows an example of a time base with prescaler ratio
equal to one.
NOTE
MCB and OPWFMB modes have different behavior.