Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 997
30.2.1 Overview
Basically the Quad Serial Peripheral Interface (QuadSPI) block serves for two different interfacing
purposes: When acting as a Serial Peripheral Interface it provides a synchronous serial bus for
communication with an external peripheral device. Alternatively the QuadSPI block can act as an interface
to a SPI serial flash device. Refer to
Section 30.2.3, QuadSPI modes of operation, for a description of the
different modes.
30.2.2 Features
When acting as SPI the QuadSPI supports the following features
• Full-duplex, three-wire synchronous transfers
• Master and Slave mode
• Buffered transmit operation using the TX FIFO with parameterized depth of 15
• Buffered receive operation using the RX FIFO with parameterized depth of 15
• Programmable transfer attributes on a per-frame basis:
— Parameterized number of transfer attribute registers (from two to eight)
— Serial clock with programmable polarity and phase
— Various programmable delays
— Programmable serial frame size of 4 to 16 bits, expandable by software control
— Continuously held chip select capability
•3 Peripheral Chip Selects
• DMA support for TX/RX path mutually exclusive with register interface. Available status
information:
— TX FIFO is not full
— RX FIFO is not empty
• 6 Interrupt conditions:
— End of queue reached
— TX FIFO is not full
— Transfer of current frame complete
— Attempt to transmit with an empty Transmit FIFO
— RX FIFO is not empty
— Frame received while RX FIFO is full
• The 6 interrupt conditions are mapped to 5 interrupt lines
• Continuous serial communications clock
When acting as interface to a serial flash device the QuadSPI supports the following features:
• Compatible with Winbond
TM
SPI Serial Flash supporting single, dual and quad mode of operation.
• One chip select signal dedicated for usage with a serial flash device.
• DMA support to read RX Buffer data via AMBA AHB bus.
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