NXP Semiconductors MPC5606S - Page 998

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
996 Freescale Semiconductor
Figure 30-1. QuadSPI block diagram
AHB Bus
IPS Bus/IPD Bus
read
read_done
AHB_Serve
fetch received
(addr, size, type)
(Data)
AHB_Control
QSPI_IC_SFM
ahbcommand
(inst, addr, size)
ready
rdata
ipcommand
(inst, addr, size)
ready
rdata
SFM Mode
ctrl_vector
ready
wdata
QSPI_IF
core clock domain
SCLK clock domain
QuadSPI Bus
ipacc
ahbacc
wdata
rdata
QSPI_IF_core
QSPI_IF_sclk
cmd
txdata
ready
tx_acc
rxdata
ready
rx_acc
events
RX
Buffer
TX
Buffer
SFAR ICR
address
register
instruct.
register
command_build
and buffer control
define
rd_data
(Addr, Cmd)
wr_data
(Data) (Data)
AHB
Buffer
IP_Ctrl
(Addr, Size)
(Data)
RX FIFO
DataDataCMD
TX FIFO
DMA and Interrupt Control
& Dataflow
Control
Command
IP_Control
Baud Rate, Delay and
Transfer Control
SPI
Shift Register
ModeMux
SO_IO1 SI_IO0
PCS[7:0]
Pad_Ctrl
TX_Data RX_Data
Ctrl_IF
QSPI_IO[3:2]
SCK
DMA and Interrupt Control
SPI Modes
Command Processing
Clock Domain Crosser
cmd
txdata
ready
tx_acc
rxdata
ready
rx_acc
events
SPI
Functionality
SFM