NXP Semiconductors MPC5606S - Handshaking with Processor

Interrupt Controller (INTC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 775
21.6.3 Handshaking with processor
21.6.3.1 Software vector mode handshaking
This section describes handshaking in software vector mode.
21.6.3.1.1 Acknowledging interrupt request to processor
A timing diagram of the interrupt request and acknowledge handshaking in software vector mode and the
handshake near the end of the interrupt exception handler, is shown in Figure 21-10. The INTC examines
the peripheral and software configurable interrupt requests. When it finds an asserted peripheral or
software configurable interrupt request with a higher priority than PRI in the associated INTC_CPR, it
asserts the interrupt request to the processor. The INTVEC field in the associated INTC_IACKR is updated
with the preempting interrupt request’s vector when the interrupt request to the processor is asserted. The
INTVEC field retains that value until the next time the interrupt request to the processor is asserted. The
rest of handshaking process is described in Section 21.4.1.1, Software vector mode.
21.6.3.1.2 End of interrupt exception handler
Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be
written.When written, the associated LIFO is popped so the preempted priority is restored into PRI of the
INTC_CPR. Before it is written, the peripheral or software configurable flag bit must be cleared so that
the peripheral or software configurable interrupt request is negated.
NOTE
To ensure proper operation across all eSys MCUs, execute an MBAR or
MSYNC instruction between the access to clear the flag bit and the write to
the INTC_EOIR.
When returning from the preemption, the INTC does not search for the peripheral or software settable
interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt
request may no longer even be asserted. When PRI in INTC_CPR is lowered to the priority of the
preempted ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software
settable interrupt request at or below that priority will not cause a preemption. Instead, after the restoration
of the preempted context, the processor will return to the instruction address that it was to next execute
before it was preempted. This next instruction is part of the preempted ISR or the interrupt exception
handler’s prolog or epilog.