NXP Semiconductors MPC5606S - Error Correction Code (ECC)

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
592 Freescale Semiconductor
Notice that when UT0.AID is low UMISR0-4, UT1-2 and bits MRE, MRV, EIE, AIS and DSI7-0 of UT0
are not accessible: reading returns undeterminate data and write has no effect.
Example 17-7. ECC logic check
UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */
UT1 = 0x55555555; /* Set DAI31-0 in UT1: Even Word Input Data */
UT2 = 0xAAAAAAAA; /* Set DAI63-32 in UT2: Odd Word Input Data */
UT0 = 0x80FF0000; /* Set DSI7-0 in UT0: Syndrome Input Data */
UT0 = 0x80FF0008; /* Set EIE in UT0: Select ECC Logic Check */
UT0 = 0x80FF000A; /* Set AIE in UT0: Operation Start */
do /* Loop to wait for AID=1 */
{ tmp = UT0; /* Read UT0 */
} while ( !(tmp & 0x00000001) );
data0 = UMISR0; /* Read UMISR0 content (expected 0x55555555) */
data1 = UMISR1; /* Read UMISR1 content (expected 0xAAAAAAAA) */
data2 = UMISR2; /* Read UMISR2 content (expected 0x55555555) */
data3 = UMISR3; /* Read UMISR3 content (expected 0xAAAAAAAA) */
data4 = UMISR4; /* Read UMISR4 content (expected 0x00FF00FF) */
UT0 = 0x00000000; /* Reset UTE, AIE and EIE in UT0: Operation End */
17.2.7.2 Error Correction Code (ECC)
The flash memory macrocell provides a method to improve the reliability of the data stored in flash
memory: the usage of an error correction code (ECC). The word size is fixed at 64 bits.
At each double word of 64 bits, there are associated 8 ECC bits that are programmed in such a way to
guarantee a Single Error Correction and a Double Error Detection (SEC-DED).
17.2.7.2.1 ECC algorithms
The flash memory macrocell supports one ECC algorithm: “All 1s No Error”. A modified Hamming code
is used that ensures the all-erased state (that is, 0xFFFF.....FFFF) data is a valid state, and will not cause
an ECC error. This allows the user to perform a blank check after a sector erase operation.
17.2.7.3 Protection strategy
Two kind of protections are available: Modify Protection to avoid unwanted program/erase in flash
memory sectors and censored mode to avoid piracy.
17.2.7.3.1 Modify protection
The flash modify protection information is stored in non-volatile flash memory cells located in the Test
flash. This information is read once during the flash initialization phase following the exit from Reset and
is stored in volatile registers that act as actuators.
The reset state of all the Volatile Modify Protection Registers is the protected state.
All the non-volatile Modify Protection registers can be programmed through a normal Double Word
Program operation at the related locations in Test flash.
The non-volatile Modify Protection registers cannot be erased.