Signal Description
MPC5606S Microcontroller Reference Manual, Rev. 7
86 Freescale Semiconductor
2. VREG HV supply (V
DDR
should be the last HV supply to ramp up; it is also OK if all HV and
generic I/O supplies including V
DDR
ramp up together)
3. LV supply
The reason for following this sequence is to ensure that when VREG releases its LVDs, the I/O and other
HV segments are powered properly. This is important because the MPC5606S does not monitor LVDs on
I/O HV supplies.
3.5 Pad types
The pads available for system pins and functional port pins are described in:
• The port pin summary table
Table 3-1. Voltage supply pin descriptions
Supply Pin Function
Pin number
144 LQFP 176 LQFP
VDD12
1
1
Decoupling capacitors must be connected between these pins and the nearest V
SS12
pin.
1.2 V core supply 42, 51, 103, 118, 133 50, 67, 123, 148, 163
VDDA 3.3 V/5 V ADC supply source 53 69
VDDE_A 3.3 V/5 V I/O supply 7, 124 7, 154, 170
VDDE_B 3.3 V/5 V I/O supply 38 46, 64
VDDE_C 3.3 V/5 V I/O supply 63 79
VDDE_E 3.3 V/5 V I/O supply 109 133
VDDMA
2
2
All stepper motor supplies need to be at same level (3.3 V or 5 V).
Motor pads 5 V supply 77 93
VDDMB
2
Motor pads 5 V supply 87 103
VDDMC
2
Motor pads 5 V supply 97 113
VDDPLL 1.2 V PLL supply 31 31
VDDR VREG reg supply 22 22
VPP
3
3
This signal needs to be connected to ground during normal operation.
9 V–12 V flash test analog write signal 26 26
VSS Digital ground 8, 23, 39, 43, 52, 64, 104,
110, 119, 125, 134
8, 23, 47, 51, 68, 80, 124,
134, 149, 155, 164, 65, 171
VSSA ADC ground 54 70
VSSMA Stepper motor ground 78 94
VSSMB Stepper motor ground 88 104
VSSMC Stepper motor ground 98 114
VSSOSC MHz oscillator ground 28 28
VSSPLL PLL ground 30 30
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