Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 951
25.4.5.3 Safe mode transition interrupt
Whenever the system enters the Safe mode as a result of a Safe mode request from the MC_RGM due to
a hardware failure, the interrupt pending bit I_SAFE of the ME_IS register is set, and an interrupt is
generated if the mask bit M_SAFE of ME_IM register is 1.
The Safe mode interrupt pending bit can be cleared only when the Safe mode request is deasserted by the
MC_RGM (see the MC_RGM chapter for details on how to clear a Safe mode request). If the system is
already in Safe mode, any new Safe mode request by the MC_RGM also sets the interrupt pending bit
I_SAFE. However, the Safe mode interrupt pending bit is not set when the Safe mode is entered by a
software request (i.e. programming of ME_MCTL register).
25.4.5.4 Mode transition complete interrupt
Whenever the system completes a mode transition fully (i.e. the S_MTRANS bit of ME_GS register
transits from 1 to 0), the interrupt pending bit I_MTC of the ME_IS register is set, and interrupt request is
generated if the mask bit M_MTC of the ME_IM register is 1. The interrupt bit I_MTC is not set when
entering low-power modes Halt and Stop in order to avoid the same event requesting the exit of these
low-power modes.
25.4.6 Peripheral clock gating
During all device modes, certain peripherals can be associated with a particular clock gating policy
determined by two groups of peripheral configuration registers.
The run peripheral configuration registers ME_RUN_PC0…7 are chosen only during the software running
modes DRUN, Test, Safe, and Run0…3. All configurations are programmable by software according to
the needs of application. Each configuration register contains a mode bit which determines whether or not
a peripheral clock is to be gated. Run configuration selection for each peripheral is done by the RUN_CFG
bit field of the ME_PCTL0…143 registers.
The low-power peripheral configuration registers ME_LP_PC0…7 are chosen only during the low-power
modes Halt, Stop, and Standby. All configurations are programmable by software according to the needs
of the application. Each configuration register contains a mode bit which determines whether or not a
peripheral clock is to be gated. Low-power configuration selection for each peripheral is done by the
LP_CFG bit field of the ME_PCTL0…143 registers.
Any modifications to the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers do not
affect the clock gating behavior until a new mode transition request is generated.
Whenever the processor enters a debug session during any mode, the following occurs for the peripheral:
• The clock is gated if the DBG_F bit of the associated ME_PCTL0…143 register is set. Otherwise,
the peripheral clock gating status depends on the RUN_CFG and LP_CFG bits. Any further
modifications of the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers
during a debug session will take effect immediately without requiring any new mode request.
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