NXP Semiconductors MPC5606S - Miscellaneous Interrupt Register (MIR)

Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 527
6. With the processor core clocks enabled, the core handles the pending interrupt request.
See Figure 16-4 and Table 16-5 for the Miscellaneous Wakeup Control Register definition.
16.4.2.5 Miscellaneous Interrupt Register (MIR)
All interrupt requests associated with ECSM are collected in the MIR register. This includes the processor
core system bus fault interrupt.
During the appropriate interrupt service routine handling these requests, the interrupt source contained in
the MIR must be explicitly cleared. See Figure 16-5 and Table 16-6.
Address: Base + 0x0013 Access: User read/write
0 1 2 3 4 5 6 7
R
ENBWCR
0 0 0
PRILVL[0:3]
W
Reset 0 1 0 0 0 0 0 0
Figure 16-4. Miscellaneous Wakeup Control (MWCR) Register
Table 16-5. Wakeup Control (MWCR) field descriptions
Name Description
0
ENBWCR
Enable WCR
0 MWCR is disabled.
1 MWCR is enabled.
4-7
PRILVL[0:3]
Interrupt Priority Level
The interrupt priority level is a core-specific definition. It specifies the interrupt priority level needed
to exit the low-power mode. Specifically, an unmasked interrupt request of a priority level greater than
the PRILVL value is required to exit the mode.
Certain interrupt controller implementations include logic associated with this priority level that
restricts the data value contained in this field to a [0, maximum – 1] range. See the specific interrupt
controller module for details.
Address: Base + 0x001F Access: User read/write
0 1 2 3 4 5 6 7
R FB0AI FB0SI FB1AI FB1SI 0 0 0 0
W w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0
Figure 16-5. Miscellaneous Interrupt Register (MIR)