NXP Semiconductors MPC5606S - UC Modes of Operation

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 257
The Datapath block provides the channel A and B registers, the internal time base, and comparators.
Multiplexors select the input of comparators and data for the register inputs, thus configuring the data path
in order to implement the channel modes. The outputs of A and B comparators are connected to the uc_ctrl
control block.
Figure 9-20. Unified Channel control and datapath block diagrams
9.5.1.1 UC modes of operation
The mode of operation of the Unified Channel is determined by the mode select bits MODE[0:6] in the
EMIOSC[n] register (see
Figure 9-20 for details).
When entering an output mode (except for GPIO mode), the output flip-flop is set to the disabled state
according to the ODIS bit in the EMIOSC[n] register.
A2
B2
B1
A1
CNT
local counter bus
global counter bus[A]
A Comparator
BSL[0]
BSL[1]+logic
BSL[1]+logic
BSL[1]+logic
internal counter
[B/C/D/E]
B Comparator
uc_datapath
uc_ctrl
control signals
input
filter
input
mode 0
logic
General
Purpose
Registers
mode 1
logic
mode n
logic
MODE
decoder
MODE
register
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