NXP Semiconductors MPC5606S - External Signal Description

Safety
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 121
Figure 4-11. SWT operation timing diagram
4.2.4 External signal description
The SWT module does not have any external interface signals.
4.2.5 Memory map and register description
The SWT programming model has seven 32-bit registers. The programming model can only be accessed
using 32-bit (word) accesses. References using a different size are invalid. Other types of invalid accesses
include: writes to read only registers, incorrect values written to the service register when enabled,
accesses to reserved addresses and accesses by masters without permission. If the RIA bit in the SWT_CR
is set, then the SWT generates a system reset on an invalid access. Otherwise, a bus error is generated. If
either the HLK or SLK bits in the SWT_CR are set then the SWT_CR, SWT_TO, and SWT_WN registers
are read-only.
Table 4-5. SWT operation after reset
SWT_CR
[WEN]
MCU mode
CPU
debug active
SWT_CR
[FRZ]
SWT operation
0 — No 0 or 1 Off
1 Normal (MC_ME modes DRUN,
Run0:3, Halt, Stop, Safe)
No 0 or 1 Running
Debug
1
(MC_ME modes DRUN,
Run0:3, Halt, Stop, Safe)
1
SWT Debug mode occurs when the processor is stopped due to user specified debug criteria such
as breakpoint.
Ye s 0 Running
Ye s 1 Halted
0 or 1 Standby No No Off
MC_ME mode
Reset phases
SWT status
SWT_CR[WEN]
Reset DRUN
Idle
Phase0
Phase1
Phase2 Phase3
Disabled
Enabled
Disabled
Enabled if WEN = 1
(see note 1)
See note 2
Notes:
1) The SWT is started on Phase1 exit and counts unconditionally during Phase2 to monitor the flash memory boot sequence.
2) Value copied from configuration bit NVUSR0[WATCHDOG_EN] in the shadow flash memory (software can modify it later)