NXP Semiconductors MPC5606S - Operation in Power Saving Modes

LCD Driver (LCD64F6B)
MPC5606S Microcontroller Reference Manual, Rev. 7
818 Freescale Semiconductor
22.5.8 Operation in power saving modes
22.5.8.1 Operation in Stop mode
The LCD64F6B system operation during Stop mode is controlled by the LCDRST bit in the LCD Control
Register (LCDCR).
If the LCD64F6B is requested to enter Stop mode and LCDRST is cleared while LCDEN is set the LCD
waveform generation clocks are stopped and the LCD64F6B drivers pull down to ground those frontplane
and backplane pins that were enabled before entering Stop mode.The contents of the LCD RAM and the
LCD registers retain the values they had prior to entering stop mode.
If LCDRST is set while LCDEN is set and the LCD64F6B is requested to enter Stop mode the LCD
waveform generation is continued.
22.5.8.2 Operation in Standby mode
See device guide for information if the LCD64F6B is powered down or stays powered in Standby mode.
The LCD64F6B system operation during Standby mode is controlled by the LCDRST bit in the LCD
Control Register (LCDCR).
If the LCD64F6B is powered down by the system, those frontplane and backplane pins goes high
impedance, that were enabled before entering Standby mode.
If the LCD64F6B is not powered down by the system, and is requested to enter Standby mode and
LCDRST is cleared while LCDEN is set the LCD waveform generation clocks are stopped and the
LCD64F6B drivers pull down to ground those frontplane and backplane pins that were enabled before
entering Standby mode.The contents of the LCD RAM and the LCD registers retain the values they had
prior to entering Standby mode.
If the LCD64F6B is not powered down by the system, and is requested to enter Standby mode and
LCDRST is set while LCDEN is set the LCD waveform generation is continued.
NOTE
The user needs to take care that the system keeps the clock applied to the
running LCD64F6B module during all modes where it is enabled. If no
clock is applied while the LCD64F6B module is running the LCD could be
damaged.
22.5.9 Other power saving
The LCD64F6B has features to adjust the frontplane and backplane drive strength and to boost the drive
strength while the planes are switching.
22.5.9.1 LCD reference clock select
Using LCDRCS the LCD reference clock can be selected. If LCDRCS is cleared, the system clock is
applied as reference clock to the prescaler input. If LCDRCS is set, the source clock for LCD Driver
system (prescaler input) is OSC clock. See device level documentation for detail on OSC clk. Selecting