NXP Semiconductors MPC5606S - Register Map

Register Map
MPC5606S Microcontroller Reference Manual, Rev. 7
1306 Freescale Semiconductor
Clock and Transfer Attribute Registers CTAR1 32-bit Base + 0x0010
Clock and Transfer Attribute Registers CTAR2 32-bit Base + 0x0014
Clock and Transfer Attribute Registers CTAR3 32-bit Base + 0x0018
Clock and Transfer Attribute Registers CTAR4 32-bit Base + 0x001C
Clock and Transfer Attribute Registers CTAR5 32-bit Base + 0x0020
Clock and Transfer Attribute Registers CTAR6 32-bit Base + 0x0024
Clock and Transfer Attribute Registers CTAR7 32-bit Base + 0x0028
Status Register SR 32-bit Base + 0x002C
DMA/Interrupt Request Register RSER 32-bit Base + 0x0030
PUSH TX FIFO Register PUSHR 32-bit Base + 0x0034
POP RX FIFO Register POPR 32-bit Base + 0x0038
DSPI Transmit FIFO Registers TXFR0 32-bit Base + 0x003C
DSPI Transmit FIFO Registers TXFR1 32-bit Base + 0x0040
DSPI Transmit FIFO Registers TXFR2 32-bit Base + 0x0044
DSPI Transmit FIFO Registers TXFR3 32-bit Base + 0x0048
Reserved — — Base +
(0x004C–0x007B
)
Receive FIFO Registers RXFR0 32-bit Base + 0x007C
Receive FIFO Registers RXFR1 32-bit Base + 0x0080
Receive FIFO Registers RXFR2 32-bit Base + 0x0084
Receive FIFO Registers RXFR3 32-bit Base + 0x0088
Reserved — — Base +
(0x0090–0x3FFF)
FlexCAN 0 Section 18.3, Memory map and register description 0xFFFC0000
Module Configuration MCR 32-bit Base + 0x0000
Control Register CTRL 32-bit Base + 0x0004
Free Running Timer TIMER 32-bit Base + 0x0008
Reserved — — Base +
(0x000C–0x000F)
Rx Global Mask Register RXGMASK 32-bit Base + 0x0010
Rx 14 Mask Register RX14MASK 32-bit Base + 0x0014
Rx 15 Mask Register RX15MASK 32-bit Base + 0x0018
Error Counter Register ECR 32-bit Base + 0x001C
Table B-2. Detailed register map (continued)
Register description Register Name
Used
Size
Address