Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1030 Freescale Semiconductor
30.4.4.1 AHB bus access considerations
It has to be noted that all logic in the QuadSPI module implementing the AHB Bus access is related to read
the content of an external serial flash device. Therefore the following restrictions apply to the QuadSPI
module with respect to accesses to the AHB bus:
• In the SPI modes all accesses to the AHB interface are served without errors and undefined values
are returned on read.
• Any write access in SFM mode is answered with the ERROR condition according to the AMBA
AHB Specification. No write occurs.
• AHB Bus access types fully supported are NONSEQ and BUSY. In fact access type BUSY is
treated in the same way like NONSEQ.
• AHB access type SEQ is treated in the same way like NONSEQ. Refer to the AMBA AHB
Specification for further details.
30.4.4.2 Memory-mapped serial flash data (QSPI_SFD)
Starting with address QSPI_AMBA_BASE the content of the external serial flash is mapped into the
address space of the device containing the QuadSPI module. Serial flash address byte address 0x0
corresponds to bus address QSPI_AMBA_BASE with increasing order. Refer to Table 30-35 below for
details.
The available address range depends from the size of the external serial flash device. Any access beyond
the size of the external serial flash provides undefined results.
Note that for serial flash devices of 128MB size the last 4 bytes are not accessible via the memory-mapped
interface.
For details concerning the read process refer to Section 30.5.3.3, Flash Read.
30.4.4.3 AHB RX Data Buffer (QSPI_ARDB)
The AHB RX Data Buffer register is used to read the buffer content of the RX Buffer. Any read access is
redirected to the RX Buffer register entry corresponding to the current value of the read pointer. The
increment of the read pointer depends from the access scheme (DMA or flag-driven). Refer to
Section 30.5.3.3.2, Host Read of the QuadSPI Module Internal Buffers, topic RX Buffer, data read via
register interface and AHB read for the description of successive accesses to the RX Buffer content.
Refer also to Section 30.5.3.4, Byte Ordering of Serial Flash Data, for the byte ordering scheme.
Table 30-35. Memory-mapped serial flash address scheme
Memory-mapped address
1
1
Access scheme is limited to 32 bit data width
Serial flash byte address
QSPI_AMBA_BASE +0x000_0000 0x000_0000 0x000_0001 0x000_0002 0x000_0003
QSPI_AMBA_BASE + 0x000_0004 0x000_0004 0x000_0005 0x000_0006 0x000_0007
... ... ... ... ...
QSPI_AMBA_BASE + 0x7FF_FFF8 0x7FF_FFF8 0x7FF_FFF9 0x7FF_FFFA 07FF_FFFB
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