NXP Semiconductors MPC5606S - Chapter 30; Glossary for Quadspi Module

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
994 Freescale Semiconductor
30.1.3 Glossary for QuadSPI module
SS Slave Select. Signal from the SPI master to the SPI slave indicating which SPI slave device the
Master want to communicate with.
w1c Write 1 to clear, writing a 1 to this field resets the flag
Table 30-3. Glossary
Term Definition
AHB Command An AHB Command is a SFM Command triggered by a read access to the address range
belonging to the memory-mapped access defined in
Tabl e 30-35. Refer to Section 30.6.6.2,
AHB bus related commands, for details.
Asserted A signal that is asserted is in its active state. An active low signal changes from logic level
one to logic level zero when asserted, and an active high signal changes from logic level zero
to logic level one.
Baud Rate Rate of data transmission in bits per second.
Clear To clear a bit or bits means to establish logic level zero on the bit or bits.
Clock Phase Determines when the data should be sampled relative to the active edge of SCK
Clock Polarity Determines the idle state of the SCK signal.
Deserialize To convert data from a serial format to a parallel format.
Drain To remove entries from a FIFO by software or hardware.
Field Two or more register bits grouped together.
FIFO entry FIFO entries and FIFO registers are used interchangeably.
Fill To add entries to a FIFO by software or hardware.
Frame The data content of a serial transmission. Also referred to as QuadSPI Data.
Host Refers to another functional block in the device containing the QuadSPI module
Instruction Code 8 bits defining the type of command to be executed.
IP Command A IP Command is a SFM Command triggered by writing into the QSPI_MCR[IC] field.
Logic level one The voltage that corresponds to Boolean true (1) state.
Logic level zero The voltage that corresponds to Boolean false (0) state.
Negated A signal that is negated is in its inactive state. An active low signal changes from logic level
0 to logic level 1 when negated, and an active high signal changes from logic level 1 to logic
level 0.
RX FIFO First-In-First-Out buffer for received data
Serialize To convert data from a parallel format to a serial format.
Set To set a bit or bits means to establish logic level one on the bit or bits.
Table 30-2. Acronyms and Abbreviations
Terms Description