NXP Semiconductors MPC5606S - Hardware Request Release Timing

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 521
2. Read back the TCD.major.e_link bit.
3. Test the TCD.major.e_link request status:
a. If the bit is set, the dynamic link attempt was successful.
b. If the bit is cleared, the attempted dynamic link did not succeed, the channel was already
retiring.
This same coherency model is true for dynamic scatter/gather operations. For both dynamic requests, the
TCD local memory controller forces the TCD.major.e_link and TCD.e_sg bits to zero on any writes to a
channel’s TCD.word7 after that channel’s TCD.done bit is set indicating the major loop is complete.
NOTE
The user must clear the TCD.done bit before writing the TCD.major.e_link
or TCD.e_sg bits. The TCD.done bit is cleared automatically by the DMA
engine after a channel begins execution.
15.5.8 Hardware request release timing
This section provides a timing diagram for deasserting the ipd_req hardware request signal. Figure 15-37
shows two read write sequences with grey indicating the release of the ipd_req hardware request signal.
Figure 15-37. ipd_req hardware handshake
rd1
wr1 rd2 wr2
hclk
htrans
AHB_AP
ipd_req
ipd_ack
ipd_done
hwrite
rd1 wr1 rd2 wr2
AHB_DP
done_lw
ipd_complete
Note: ipd_req must de-assert in this cycle unless another service request is intended