Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 943
registers, the MC_ME requests the MC_PCU to turn on the regulator and waits for the output voltage
stable status in order to update the S_MVR bit of the ME_GS register.
This step is required only during the exit of the low-power modes Halt and Stop. In this step, the fast
internal RC oscillator (16MHz) is switched on regardless of the target mode configuration, as the main
voltage regulator requires the 16MHz int. RC osc. during startup in order to generate the voltage status.
During the Standby exit sequence, the MC_PCU alone manages the startup of the main voltage regulator,
and the MC_ME is kept in Reset or shut off (depending on the power domain #1 status).
25.4.3.8 Flash Modules Switch-On
On completion of the Main Voltage Regulator Switch-On, if a flash module needs to be switched to normal
mode from its low-power or power-down mode based on the CFLAON and DFLAON bit fields of the
ME_<current mode>_MC and ME_<target mode>_MC registers, the MC_ME requests the flash to exit
from its low-power/power-down mode. When the flash modules are available for access, the S_CFLA and
S_DFLA bit fields of the ME_GS register are updated to “11” by hardware.
If the main regulator is also off in device low-power modes, then during the exit sequence, the flash is kept
in its low-power state and is switched on only when the Main Voltage Regulator Switch-On process has
completed.
WARNING
It is illegal to switch the flashes from low-power mode to power-down mode
and from power-down mode to low-power mode. The MC_ME, however,
does not prevent this nor does it flag it.
25.4.3.9 FMPLL0 Switch-On
On completion of the Clock sources switch-on and Main Voltage Regulator Switch-On, if the FMPLL0 is
to be switched on from the off state based on the FMPLL0ON bit of the ME_<current mode>_MC and
ME_<target mode>_MC registers, the MC_ME requests the FMPLL0 digital interface to start the phase
locking process and waits for the FMPLL0 to enter into the locked state. When the FMPLL0 enters the
locked state and starts providing a stable output clock, the S_FMPLL0 bit of ME_GS register is set.
25.4.3.10 Power Domain #2 Switch-On
On completion of the Main Voltage Regulator Switch-On, the MC_ME indicates a mode change to the
MC_PCU. The MC_PCU then determines whether a startup sequence is required for power domain #2.
Only after the MC_PCU has executed all required startups does the MC_ME complete the mode transition.
25.4.3.11 Pad Outputs-On
On completion of the Main Voltage Regulator Switch-On, if the PDO bit of the ME_<target mode>_MC
register is cleared, then
• All pad outputs are enabled to return to their previous state
• The I/O pads power sequence driver is switched on
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