NXP Semiconductors MPC5606S - Power-Down Mode

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 599
The flash module uses reset to initialize register and status bits to their default reset values.
If the flash module is executing a Program or Erase operation (MCR.PGM = 1 or MCR.ERS = 1) and a
reset is issued, the operation will be terminated and the module will disable the high voltage logic without
damage to the high voltage circuits. Reset terminates all operations and forces the flash module into User
mode, ready to receive accesses. Reset and power-off must not be used systematically to terminate a
Program or Erase operation.
After reset is negated, read register access may be done, although it should be noted that registers that
require updating from shadow information, or other inputs, may not read updated values until
MCR.DONE transitions. MCR.DONE may be polled to determine if the flash module has transitioned out
of reset. Notice that the registers cannot be written until MCR.DONE is high.
17.3.5.2 Power-Down mode
The Power-Down mode turns off all flash memory DC current sources, so that power dissipation is due
only to leakage.
In Power-Down mode no reads from or write to the Module are possible.
The user may not read some registers (UMISR0-4, UT1-2 and part of UT0) until the Disable mode is
exited. On the contrary write access is locked on all the registers in Power-Down mode.
When enabled the flash module returns to its previous state in all cases unless in the process of executing
an erase high voltage operation at the time of entering Power-Down mode.
If the flash memory module enters Power-Down mode during an erase operation, the MCR[ESUS] bit is
set. The user may resume the erase operation when the module exits Power-Down mode by clearing the
MCR[ESUS] bit. MCR[EHV] must be high to resume the erase operation.
If the flash memory module is configured to enter Power-Down mode during a program operation, the
operation will be completed and the Power-Down mode will be entered only after the programming ends.
If the flash memory module is put in Power-Down mode and the Vector Table remains mapped in the flash
memory address space, the user must take care that the flash memory macrocell will strongly increase the
interrupt response time by adding several wait states.
It is forbidden to enter Low-Power mode when the Power-Down mode is active.
17.3.5.3 Low-Power mode
The Low-Power mode turns off most of the DC current sources within the flash memory module.
The module (flash core and registers) is not accessible for read or write after it enters Low-Power mode.
The wakeup time from Low-Power mode is faster than the wakeup time from Power-Down mode.
The user may not read some registers (UMISR0-4, UT1-2 and part of UT0) until the Low-Power mode is
exited. Write access is locked on all the registers in Low-Power mode.