Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 741
Reading the IBDR will return the last byte received while the I
2
C is configured in either master receive or
slave receive modes. The IBDR does not reflect every byte that is transmitted on the I
2
C bus, nor can
software verify that a byte has been written to the IBDR correctly by reading it back.
In master transmit mode, the first byte of data written to the IBDR following assertion of MS/SL is used
for the address transfer and should comprise the calling address (in position D7–D1) concatenated with the
required R/W bit (in position D0).
20.4.3.6 I
2
C Bus Interrupt Configuration Register
20.5 Functional description
20.5.1 General
This section provides a complete functional description of the Inter-Integrated Circuit (I
2
C).
20.5.2 I-Bus Protocol
The I
2
C Bus system uses a Serial Data line (SDA) and a Serial Clock Line (SCL) for data transfer. All
devices connected to it must have open drain or open collector outputs. A logical AND function is
exercised on both lines with external pullup resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer and stop signal. They are described briefly in the following sections and illustrated in
Figure 20-10.
Offset 0x0005 Access: User read/write
0 1 2 3 4 5 6 7
R BIIE 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0
Figure 20-9. I
2
C Bus Interrupt Configuration Register (IBIC)
Table 20-10. IBIC field descriptions
Field Description
BIIE Bus Idle Interrupt Enable bit. This configuration bit can be used to enable the generation of an interrupt
once the I
2
C bus becomes idle. Once this bit is set, an IBB high-low transition will set the IBIF bit. This
feature can be used to signal to the CPU the completion of a stop on the I
2
C bus.
0 Bus Idle Interrupts disabled
1 Bus Idle Interrupts enabled
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