Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
740 Freescale Semiconductor
20.4.3.5 I
2
C Bus Data I/O Register
In master transmit mode, when data is written to IBDR, a data transfer is initiated. The most significant bit
is sent first. In master receive mode, reading this register initiates next byte data receiving. In Slave mode,
the same functions are available after an address match has occurred. Note that the Tx/
Rx bit in the IBCR
must correctly reflect the desired direction of transfer in master and Slave modes for the transmission to
begin. For instance, if the I
2
C is configured for master transmit but a master receive is desired, then reading
the IBDR will not initiate the receive.
IBAL Arbitration Lost. The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost.
Arbitration is lost in the following circumstances:
• SDA is sampled low when the master drives a high during an address or data transmit cycle.
• SDA is sampled low when the master drives a high during the acknowledge bit of a data receive cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in Slave mode.
• A stop condition is detected when the master did not request it.
This bit must be cleared by software, by writing a one to it. A write of zero has no effect.
SRW Slave Read/Write. When IAAS is set, this bit indicates the value of the R/W command bit of the calling
address sent from the master. This bit is only valid when the I-Bus is in Slave mode, a complete address
transfer has occurred with an address match and no other transfers have been initiated. By programming
this bit, the CPU can select slave transmit/receive mode according to the command of the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
IBIF I-Bus Interrupt Flag. The IBIF bit is set when one of the following conditions occurs:
• Arbitration lost (IBAL bit set)
• Byte transfer complete (TCF bit set)
• Addressed as slave (IAAS bit set)
• NoAck from Slave (MS and Tx bits set)
•I
2
C Bus going idle (IBB high-low transition and enabled by BIIE)
A processor interrupt request will be caused if the IBIE bit is set. This bit must be cleared by software, by
writing a one to it. A write of zero has no effect on this bit.
RXAK Received Acknowledge. This is the value of SDA during the acknowledge bit of a bus cycle. If the received
acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion
of 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the
9th clock.
0 Acknowledge received
1 No acknowledge received
Offset 0x0004 Access: User read/write
0 1 2 3 4 5 6 7
R
DATA
W
Reset 0 0 0 0 0 0 0 0
Figure 20-8. I
2
C Bus Data I/O Register (IBDR)
Table 20-9. IBSR field descriptions (continued)
Field Description
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