Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 739
20.4.3.4 I
2
C Bus Status Register
RSTA Repeat Start. Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the
current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if
the bus is owned by another master, will result in loss of arbitration.
0 No effect
1 Generate repeat start cycle
DMAEN DMA Enable. When this bit is set, the DMA TX and RX lines will be asserted when the I
2
C module requires
data to be read or written to the data register. No Transfer Done interrupts will be generated when this bit
is set, however an interrupt will be generated if the loss of arbitration or addressed as slave conditions
occur. The DMA mode is only valid when the I
2
C module is configured as a Master and the DMA transfer
still requires CPU intervention at the start and the end of each frame of data. See tSection 15.5,
Initialization/application information, for more details.
0 Disable the DMA TX/RX request signals
1 Enable the DMA TX/RX request signals
Offset 0x0003 Access: Read-only any time
1
1
With the exception of IBIF and IBAL, which are software clearable.
0 1 2 3 4 5 6 7
R TCF IAAS IBB IBAL 0 SRW IBIF RXAK
W w1c w1c
Reset 1 0 0 0 0 0 0 0
Figure 20-7. I
2
C Bus Status Register (IBSR)
Table 20-9. IBSR field descriptions
Field Description
TCF Transfer complete. While one byte of data is being transferred, this bit is cleared. It is set by the falling edge
of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer
to the I
2
C module or from the I
2
C module.
1 Transfer complete
0 Transfer in progress
IAAS Addressed as a slave. When its own specific address (I-Bus Address Register) is matched with the calling
address, this bit is set. The CPU is interrupted provided the IBIE is set. Then the CPU needs to check the
SRW bit and set its Tx/
Rx mode accordingly. Writing to the I-Bus Control Register clears this bit.
0 Not addressed
1 Addressed as a slave
IBB Bus busy. This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a stop
signal is detected, IBB is cleared and the bus enters idle state.
0 Bus is Idle
1Bus is busy
Table 20-8. IBCR field descriptions (continued)
Field Description
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