NXP Semiconductors MPC5606S - DMA Error (DMAERRH, DMAERRL) Registers

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 491
15.3.1.14 DMA Error (DMAERRH, DMAERRL) registers
The DMAERR{H,L} registers provide a bit map for the implemented channels {16,32,64} signaling the
presence of an error for each channel. DMAERRH supports channels 63–32, while DMAERRL covers
channels 31–00. The DMA engine signals the occurrence of a error condition by setting the appropriate
bit in this register. The outputs of this register are enabled by the contents of the DMAEEI register, then
logically summed across groups of 16, 32, and 64 channels to form several group error interrupt requests
which is then routed to the platform’s interrupt controller. During the execution of the interrupt service
routine associated with any DMA errors, it is software’s responsibility to clear the appropriate bit, negating
the error interrupt request. Typically, a write to the DMACERR register in the interrupt service routine is
used for this purpose. Recall the normal DMA channel completion indicators, setting the transfer control
descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is
detected.
The contents of this register can also be polled and a non-zero value indicates the presence of a channel
error, regardless of the state of the DMAEEI register. The state of any given channel’s error indicators is
affected by writes to this register; it is also affected by writes to the DMACERR register. On writes to the
DMAERR, a one in any bit position clears the corresponding channel’s error status. A zero in any bit
position has no effect on the corresponding channel’s current error status. The DMACERR register is
provided so the error indicator for a single channel can easily be cleared. See Figure 15-18, Figure 15-19,
and Table 15-15 for the DMAERR definition.
Address: Base + 0x0024 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INT
31
INT
30
INT
29
INT
28
INT
27
INT
26
INT
25
INT
24
INT
23
INT
22
INT
21
INT
20
INT
19
INT
18
INT
17
INT
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INT
15
INT
14
INT
13
INT
12
INT
11
INT
10
INT
09
INT
08
INT
07
INT
06
INT
05
INT
04
INT
03
INT
02
INT
01
INT
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-17. DMA Interrupt Request Low (DMAINTL) register
Table 15-14. DMA Interrupt Request (DMAINTH, DMAINTL) field descriptions
Name Description
INTn,
n = 0,... 15
n = 0,... 31
n = 0,... 63
DMA Interrupt Request n
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.