NXP Semiconductors MPC5606S - Receive First in First out (RX FIFO) Buffering Mechanism

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1035
The TX FIFO Counter field (TXCTR) in the SPI Status Register (QSPI_SPISR) indicates the number of
valid entries in the TX FIFO. The TXCTR is updated every time the QuadSPI _PUSHR is written or SPI
data is transferred into the shift register from the TX FIFO.
The TXNXTPTR field indicates which TX FIFO Entry will be transmitted during the next transfer. The
TXNXTPTR contains the positive offset from QSPI_TXFR0 in number of 32-bit registers. For example,
TXNXTPTR equal to two means that the QSPI_TXFR2 contains the SPI data and command for the next
transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the
shift register.
30.5.2.5.1 Filling the TX FIFO
Host software or other intelligent blocks can add (push) entries to the TX FIFO by writing to the
QSPI_PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in the QSPI_SPISR is set.
The TFFF bit is cleared when TX FIFO is full and the DMA controller indicates that a write to
QSPI_PUSHR is complete or by host software writing a 1 to the TFFF in the QSPI_SPISR. The TFFF can
generate a DMA request or an interrupt request. See Section 30.5.3.5.1, Transmit buffer fill interrupt
request, for details.
The QuadSPI ignores attempts to push data to a full TX FIFO, i.e., the state of the TX FIFO is unchanged.
No error condition is indicated.
30.5.2.5.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the
TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO Counter
is decremented by one. At the end of a transfer, the TCF bit in the QSPI_SPISR is set to indicate the
completion of a transfer. The TX FIFO is cleared by writing a 1 to the CLR_TXF bit in QSPI_MCR.
If an external bus master initiates a transfer with a QuadSPI slave while the slave’s QuadSPI TX FIFO is
empty, the Transmit FIFO Underrun Flag (TFUF) in the slave’s QSPI_SPISR is set. See Section
Section 30.5.2.10.4, Transmit FIFO Underrun Interrupt Request, for details.
30.5.2.6 Receive First In First Out (RX FIFO) Buffering Mechanism
The RX FIFO functions as a buffer for data received on the SI pin. The RX FIFO holds in total 15 received
SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer when the received data
in the shift register is transferred into the RX FIFO. SPI data are removed (popped) from the RX FIFO by
reading the
POP RX FIFO Register (QSPI_POPR). RX FIFO entries can only be removed from the RX
FIFO by reading the QSPI_POPR or by flushing the RX FIFO.
The RX FIFO Counter field (RXCTR) in the SPI Status Register (QSPI_SPISR) indicates the number of
valid entries in the RX FIFO. The RXCTR is updated every time the QSPI_POPR is read or SPI data is
copied from the shift register to the RX FIFO.
The POPNXTPTR field in the QSPI_SPISR points to the RX FIFO entry that is returned when the
QSPI_POPR is read. The POPNXTPTR contains the positive offset from QSPI_RXFR0 in number of
32-bit registers. For example, POPNXTPTR equal to two means that the QSPI_RXFR2 contains the