NXP Semiconductors MPC5606S - Register Description

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
214 Freescale Semiconductor
8.7.3 Register description
Note: The LPRC_CTL register is writable only in supervisor mode.
8.8 FIRC digital interface
8.8.1 Introduction
The FIRC digital interface controls the main internal 16 MHz RC oscillator (FIRC). It holds control and
status registers that are accessible by software.
8.8.2 Functional description (16 MHz)
The main RC oscillator provides a high-frequency (f
MRC
) clock. This clock can be used to fasten the exit
from reset and wakeup sequence from low-power modes of the system. It is controlled by the MC_ME
module based on the current device mode. The clock source status is updated in the S_RC bit of the
ME_GS register. Please refer to Chapter 25, Mode Entry Module (MC_ME), for further details.
The MRC clock can be further divided by a configurable division factor in the range 1 to 32 to generate
the divided clock to match system requirements. This division factor is specified by the RCDIV[4:0] bits
of the RC_CTL register.
Base Address: 0xC3FE_0080 Offset: 0x0000 Access: Supervisor: read/write, User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0
LPRCTRIM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0
LPRCDIV
0 0 0
S_LPR
C
0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-21. Low-Power RC Control Register (LPRC_CTL)
Table 8-18. Low-Power RC Control Register (LPRC_CTL) field descriptions
Field Description
11–15
LPRCTRIM[4:0]
Low-power RC trimming bits
Note: Not all configurations can be used. Please refer to the MPC5606S .
19–23
LPRCDIV[4:0]
Low-power RC clock division factor
These bits specify the low-power RC oscillator output clock division factor. The output clock is
divided by the factor LPRCDIV + 1.
27
S_LPRC
Low-power RC clock status
0 LPRC is not providing a stable clock.
1 LPRC is providing a stable clock.