NXP Semiconductors MPC5606S - Threshold Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
370 Freescale Semiconductor
12.3.4.18 Threshold Register
Figure 12-20 represents the Threshold Register.
Table 12-21. SYN_POL field descriptions
Field Description
21
INV_PDI_DE
Polarity change of PDI input data Enable.
0 DE is active high
1 DE is active low
22
INV_PDI_HS
Polarity change of PDI input HSYNC.
0 HSYNC is active high
1 HSYNC is active low
23
INV_PDI_VS
Polarity change of PDI input VSYNC.
0 VSYNC is active high
1 VSYNC is active low
24
INV_PDI_CLK
Polarity change of PDI input Clock.
0 DCU samples data on the rising edge
1 DCU samples data on the falling edge
25
INV_PXCK
Polarity change of Pixel Clock.
0 Display samples data on the falling edge
1 Display samples data on the rising edge
26
NEG
Indicates if value at the output (pixel data output) needs to be negated.
0 Output is to remain same
1 Output to be negated
27
BP_VS
Bypass Vertical Synchronize Signal (internal pin muxing).
0 Do not bypass VSYNC signal output
1 CSYNC bypass VSYNC signal, output CSYNC instead of VSYNC
28
BP_HS
Bypass Horizontal Synchronize Signal (internal pin muxing).
0 Do not bypass HSYNC signal output
1 CSYNC bypass HSYNC signal, output CSYNC instead of HSYNC
29
INV_CS
Invert Composite Synchronize Signal.
0 Do not invert CSYNC signal, active HIGH
1 Invert CSYNC signal, active LOW
30
INV_VS
Invert Vertical Synchronize Signal
0 Do not invert VSYNC signal, active HIGH
1 Invert VSYNC signal, active LOW
31
INV_HS
Invert Horizontal Synchronize Signal.
0 Do not invert HSYNC signal, active HIGH
1 Invert HSYNC signal, active LOW