Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
366 Freescale Semiconductor
12.3.4.13 BGND Register
Figure 12-15 represents the BGND register.
18
PDI_EN
Enables the PDI
0 Disabled
1 Enabled
19
PDI_BYTE_REV
Controls the byte ordering in Narrow mode
0 LSB is followed by MSB data
1 MSB is followed by LSB data
20
PDI_DE_MODE
Enables the PDI data Enable mode. Here Data Enable is treated as an input.
0 Value on data Enable signal is ignored
1 Data enable signal must be present in incoming stream
21
PDI_NARROW_M
ODE
Enables the PDI Narrow mode (refer to Section 12.8.2.4, Normal and Narrow mode)
0 Narrow mode is disabled
1 Narrow mode is enabled
22–23
PDI_MODE
Defines the different modes in which PDI is operating
00 8-bit monochrome data input
01 16-bit RGB 565 format
10 18-bit RGB 666 data format.
11 YCbCr data in 4:2:2 format.
24
PDI_SLAVE_MOD
E
Enables PDI Slave mode
0 Disabled
1 Enabled
25
TAG_ EN
Enables the calculation of CRC only on the safety layers
0 CRC calculated over the whole area of interest (area of interest given by SIG_DESC
registers)
1 Calculates CRC only on safety enabled layers
26
SIG_EN
Enables the signature calculator block
0 Signature calculator is disabled
1 Signature calculator is enabled
27
PDI_SYNC
Decides whether the PDI uses external or internal synchronization.
0 External Synchronization. The PDI receives the SYNC (hsync, vsync) signals from external
source.
1 Internal Synchronization. PDI extracts the SYNC information from the digital data.
29
EN_GAMMA
Enables/Disables the Gamma correction
0 Gamma correction is disabled
1 Gamma correction is enabled
30–31
DCU_MODE
DCU operating mode and pixel clock enable
00 DCU off
01 Normal mode. Pixel clock active and panel content controlled by layer configuration
10 Test mode. Panel content fetched from CLUT/Tile memory
11 Color Bar Generation. Pixel clock active and panel content controlled by color bar registers.
Table 12-16. DCU_MODE field descriptions (continued)
Field Description
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